A Scalable Software Defined Network Orchestrator for Photonic Network on Chips

Photonic networks and software-defined are two promising technologies to improve network-on-chips performance, scalability, resource utilization. Several architectures suffer from scaling limitations, high-power consumption, noise interference drawbacks. In this paper, an enhanced photonic network-on-chip architecture called (SD-PNoC) is presented. The proposed based on a hybrid hardware-software approach, Software-Defined Management Orchestrator (SDMO) separate the network control data forwarding planes. This orchestrator has hosted upper hardware router as virtual layer capable of dynamic management. It reconfigures paths allows execution different algorithms in real-time, it scales topology both applications requirements. SD-PNoC architecture, hierarchical communication protocols, management policies were implemented, simulated, tested using customized Phoenix-SIM framework OMNIT++ simulation environment. Numerous experiments under conditions have been performed proven that performance better than conventional electronic chip (ENoC). Furthermore, results without showed latency reduced by 46% 25.5% for $4\times 4$ $8\times 8$ structures, respectively. While power consumption 76.5% 78.5% Besides, area 33.4%. Moreover, SDMO with structures increased enhancement 37.3% approximately 80%, which assure ability remarkably enhance overall complex structures.